1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a controller, a semiconductor memory system and an operating method thereof.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile memory devices, such as dynamic random access memory (DRAM) and static RAM (SRAM), and nonvolatile memory devices, such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), ferromagnetic RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM) and flash memory.
Volatile memory devices lose their data without a constant source of power, whereas nonvolatile memory devices are able to retain their data. In particular, flash memory devices are widely used as storage mediums in computer systems because of their high program speed, low power consumption and large data storage capacity.
In nonvolatile memory devices, especially in flash memory devices, data states of each memory cell are determined based on the number of bits of data stored in the memory cell. A memory cell storing 1-bit data is called a single-bit cell or a single-level cell (SLC). A memory cell storing multi-bit data (i.e., 2 or more bits of data) is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. The multi-bit cell is advantageous for high integration. However, as the number of bits of data programmed in each memory cell increases, the reliability of the data decreases and the read failure rate of the data increases.
For example, when k-bit information is to be programmed in a memory cell, one of 2k threshold voltages is formed in the memory cell. Due to minute differences between the electrical characteristics of memory cells, the threshold voltages of memory cells programmed with the same data form a threshold voltage distribution. Threshold voltage distributions correspond to 2k data values corresponding to the k-bit information, respectively.
However, the voltage window available for each threshold voltage distribution is limited. Therefore, as the value k increases, the distance between the threshold voltage distributions decreases and the adjacent threshold voltage distributions overlap. As the adjacent threshold voltage distributions overlap, read data may include error bits.
FIG. 1 is a threshold voltage distribution diagram schematically illustrating program and erase states of a 3-bit multi-level cell (3-bit MLC) in a nonvolatile memory device.
FIG. 2 is a threshold voltage distribution diagram schematically illustrating program and erase states of a 3-bit MLC having deteriorated characteristics in a nonvolatile memory device.
In an MLC nonvolatile memory device, e.g., an MLC flash memory device in which k-bit data is programmed in a memory cell, the memory cell may have one of 2k threshold voltage distributions. For example, a 3-bit MLC has one of 8 threshold voltage distributions.
Threshold voltages of memory cells programmed with the same data form the threshold voltage distribution due to characteristic differences between the memory cells. In a 3-bit MLC nonvolatile memory device, as illustrated in FIG. 1, threshold voltage distributions corresponding to 7 program states ‘P1’ to ‘P7’ and an erase state ‘E’ are formed. FIG. 1 shows an ideal case in which threshold voltage distributions do not overlap and have read voltage margins therebetween.
Referring to the flash memory example of FIG. 2, a memory cell may experience charge loss, where electrons trapped at a floating gate or tunnel oxide film are discharged over time. Such charge loss may accelerate when the tunnel oxide film deteriorates by iterative program and erase operations. Charge loss results in a decrease in the threshold voltages of memory cells. For example, as illustrated in FIG. 2, the threshold voltage distribution may be shifted left due to charge loss.
Further, program disturbance, erase disturbance and/or back pattern dependency also cause increases in threshold voltages. As characteristics of memory cells deteriorate, as described above, threshold voltage distributions of adjacent states may overlap, as illustrated in FIG. 2.
Once threshold voltage distributions overlap, read data may include a significant number of errors when a particular read voltage is applied to a selected word line. For example, when a memory cell is sensed in an ‘on’ state by a read voltage Vread3 that is applied to a selected word line, the memory cell is determined to have a second program state ‘P2’. When a memory cell is sensed as an ‘off’ state by a read voltage Vread3 applied to a selected word line, the memory cell is determined to have a third program state ‘P3’. However, when threshold voltage distributions overlap, the memory cell, which actually has the third program state ‘P3’, may be erroneously determined to have the second program state ‘P2’. In short, when the threshold voltage distributions overlap as illustrated in FIG. 2, read data may include a significant number of errors.
What is therefore required is a scheme for reducing failure of read operations for data stored in memory cells of a semiconductor memory device.